The present invention relates to a cache memory control circuit.
A cache memory works to reduce the time required for obtaining data, and is widely employed as means to enhance performance of a processor. A computer employing a cache memory has been disclosed, for example, in "AFIPS", Vol. 45, pp. 749, 1976.
In recent years, a cache memory has been employed even in microprocessors, and when required data has not been contained in the cache memory, the data or a data block containing the data must be fetched from the main memory. The fetching, however, is carried out requiring ordinary fetching time as well as reference time to determine whether the data is contained in the cache memory or not. Therefore, if the probability (hereinafter referred to as hit rate) in which the necessary data exists in the cache memory is low, it becomes difficult to enhance the performance of the system as expected, but rather the retrieval time turns out to be overhead and, in extreme cases, performance is often deteriorated. As for instructions, in general, the same instruction is in many cases accessed many times since data is usually localized in a relatively small area. Therefore, a high hit ratio may be obtained even with the cache memory of a relatively small capacity. In the case of an operand, however, the locality is relatively weak, so that a high hit ratio is not effectively obtained unless the cache memory has a capacity which is relatively large. For this reason, even a minicomputer is usually provided with a cache memory having a capacity of about four kilobytes.
However, in a very small processor such as a microprocessor, the time for sending and receiving data relative to an external unit is considerably longer than the time for effecting such operations in the chip. Therefore, it has been strongly desired to form a cache memory in the same chip as the CPU. With the current integration degree of LSIs, however, it is difficult to form a cache memory of a large capacity on the same chip as the CPU. At present, therefore, the capacity of about 500 bytes is a limit, Therefore, a contrivance is necessary to obtain a high hit rate even with the cache memory of a small capacity.